The present invention relates, in general, to the field of integrated circuit memory devices and those devices incorporating embedded memory arrays. More particularly, the present invention relates to a refresh initiated precharge technique using look-ahead refresh of especial utility with respect to dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), synchronous DRAM (xe2x80x9cSDRAMxe2x80x9d), specialty DRAM and embedded DRAM and SDRAM integrated circuit (xe2x80x9cICxe2x80x9d) devices.
It has long been a goal of memory design to increase the performance of DRAM in order to support higher speed processors. One method of increasing DRAM performance is to increase the xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d data rate across the memory bus. SDRAM access times and burst data rates are constantly improving by manufacturing process xe2x80x9cshrinksxe2x80x9d and improved interconnect technology. Additionally, improved command bus utilization has been achieved by reducing the number of instructions needed to perform certain memory operations. In general, the fewer command cycles which are required for the execution of memory commands results in more bus cycles which are then available for memory data transfers.
To date, several approaches have been used to minimize the number of command cycles needed to access SDRAM devices and embedded arrays. One example is the use of xe2x80x9cburst accessesxe2x80x9d which utilize a single xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d command execution in order to read or write to multiple sequential words. Another technique for reducing the number of command cycles required to access SDRAMs is the use of an xe2x80x9cauto-prechargexe2x80x9d mode of operation. Auto-precharge is a programmable mode wherein a xe2x80x9cprechargexe2x80x9d operation automatically occurs at the end of a predetermined number of burst xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d cycles without requiring the assertion of an external xe2x80x9cprechargexe2x80x9d command. Similarly, the execution of a xe2x80x9crefreshxe2x80x9d command in SDRAMs results in the device automatically precharging at the end of the xe2x80x9crefreshxe2x80x9d operation.
A xe2x80x9crefreshxe2x80x9d or xe2x80x9cactivexe2x80x9d command can occur on any clock cycle in an integrated circuit memory, requiring internal (on-chip) detection of the cycle type being executed. This detection process slows down the row address path within the device. On-chip refresh circuitry has been incorporated in DRAM designs for several decades. When first introduced, a separate refresh pin was used to inform the DRAM to execute a refresh operation using internally generated addresses instead of a normal, externally supplied row address. Later, /CAS-before-/RAS (CAS=column address strobe, and RAS=row address strobe) commands were used to enable on-chip refresh cycles. When /CAS was xe2x80x9chighxe2x80x9d and /RAS went xe2x80x9clowxe2x80x9d, a normal row selection was done using the external address supplied to the time when /RAS went xe2x80x9clowxe2x80x9d. However, if /CAS was xe2x80x9clowxe2x80x9d when /RAS went xe2x80x9clowxe2x80x9d, then a refresh operation was executed using an internally generated refresh address.
Conventional SDRAMs currently support two different types of refresh operations: auto-refresh and self-refresh. Auto-refresh uses a specific command instruction: /CS (chip select), /RAS, and /CAS xe2x80x9clowxe2x80x9d with /WE (write enable) xe2x80x9chighxe2x80x9d that is sampled at the rising edge of the DRAM""s input clock signal. The self-refresh command is similar to auto-refresh, but occurs concurrently with entering power-down mode. In self-refresh operation, the device periodically executes refresh cycles (which are self-timed) to maintain stored data integrity during power-down mode.
In the past, incorporating on-chip refresh techniques using the methods described above, had little impact on device performance. However, as the operating frequency of DRAMs and SDRAMs has increased, the inclusion of on-chip refresh using conventional methods has had an impact on row access performance. With present methods, during any cycle that an active command can be executed, a refresh command could have been executed instead, provided the device had been previously idle (in precharge state.) For this reason, the on-chip circuitry must hold-off row selection while the appropriate address is selected, depending on whether the present instruction is an xe2x80x9cactivexe2x80x9d or a xe2x80x9crefreshxe2x80x9d command. This process is complicated in most instances and a command address latch is used to hold either the externally supplied row address or the internally generated address from the refresh address counter depending on the command. As clock rate increases, the operational time penalty due to selecting which address to use before row selection can be enabled will become a larger percentage of the row select time.
Further, with conventional DRAM-based memory technology, open memory banks must be closed prior to the issuance of a xe2x80x9crefreshxe2x80x9d command. These banks are required to be closed by issuing individual xe2x80x9cprechargexe2x80x9d commands to open banks using a xe2x80x9cprecharge allxe2x80x9d to close open banks or xe2x80x9cauto-prechargexe2x80x9d commands for xe2x80x9creadxe2x80x9d or xe2x80x9cwritexe2x80x9d cycles to ensure that an opened bank has been closed (or precharged) prior to issuing a refresh command.
A refresh initiated precharge technique using look-ahead refresh eliminates the need to close banks in a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) array prior A to executing a xe2x80x9crefreshxe2x80x9d command by taking advantage of the fact that the actual initiation of an internal xe2x80x9crefreshxe2x80x9d operation is delayed by at least one clock cycle from the execution of the external xe2x80x9crefreshxe2x80x9d command. The technique is effectuated through the issuance of a xe2x80x9crefreshxe2x80x9d command to cause all banks within the DRAM array to precharge. This precharge occurs prior to the n-cycle delay (where N=1 or more clock cycles) of the internal xe2x80x9crefreshxe2x80x9d operation.
Consequently, it is then unnecessary to execute specific xe2x80x9cprechargexe2x80x9d commands to close all open banks prior to executing the xe2x80x9crefreshxe2x80x9d command which frees otherwise consumed instruction bus bandwidth and guarantees that all banks have been precharged (are idle; a required condition) prior to the initiation of on-chip refresh operations. In this manner, the requirement for precharging all banks is automatically satisfied and the associated controller design may be concomitantly simplified.
Particularly disclosed herein is a method and means for initiating precharge operations to at least one bank of a dynamic random access memory array. The method comprises: supplying a refresh command to the memory array; substantially concurrently precharging the memory array bank in response to the refresh command; and initiating refresh operations to the memory bank at least one clock cycle following the step of supplying the refresh command.
Also disclosed herein is an integrated circuit device including a dynamic random access memory array which comprises: a refresh command input for receiving a refresh command signal thereon; and control logic coupled to receive the refresh command signal for initiating a refresh operation on at least a portion of the memory array in response thereto. The control logic is further operational for initiating a precharge operation to at least one bank of the memory array substantially concurrently with receipt of the refresh command signal.